The continuous development of complex applications which incorporate analog and digital components on a single chip, together with the rapid growth of the integration level and the remarkable impact of process variability on modern technologies contribute to increase the sensitivity of circuit performance to the inherent fluctuations of the fabrication process parameters. The combined action of these components leads to an increased spread in the performance of VLSI circuits and, thus, significant parametric yield losses.
Therefore parametric faults, which result from global variations in manufacturing, are becoming more important for mixed signal IC blocks as well as their detection, particularly during the early stages of the development process. Unlike the case for digital circuits where efficient design for testability techniques have been developed to increase signal controllability and the detection of internal nodes, analog circuits still require long production testing time and expensive test equipment in order to verify all circuit specifications. Furthermore, the low sensitivity to the internal signal of analog component nodes makes it more difficult to diagnose faulty circuits or measure the functions of embedded components. As a matter of fact, these problems cannot be solved by simply introducing additional circuitry to achieve controllability and the detection capability of analog nodes, since this can significantly perturb their impedance and affect the performance of the block under test.
Another simplification of digital compared to analog testing is the availability of easy fault models such as “stuck at” faults, which stem from the dominance of short and opens mechanisms. In mixed signal applications, parametric faults are at least as important as random and systematic defects, therefore simplified models for the detection of catastrophic faults cannot be applied. Finally, digital test program development can be automated with the support of Automatic Test Pattern Generators (ATPG) and verified with software and hardware description of the circuit before the first silicon is available. However, analog test development still requires manual optimization steps and an efficient synergic interaction between the design, process and test development teams. Consequently, the delay in the availability of prototypes and the lack of automation for analog test program development can strongly penalize the time to market and affect investments returns. Therefore, the need for efficient testing methods for mixed signal embedded IC components with respect to parametric faults increases, however an exhaustive functional testing results in an extremely expensive procedure.
Parametric variations are the major concern for testing analog and mixed signal integrated circuits (Ics) and embedded components, because they are likely to occur and harder to detect. Therefore, parametric testing of analog and mixed signal circuits is a topic of growing interest. Different approaches have been proposed to (i) minimize testing time by optimally reordering the process control monitor electrical test (PCM/e-test) measurements, (ii) drop functional tests without degrading fault coverage, (iii) identify optimal test sets for ICs and (iv) to evaluate their effectiveness.
L. Milor and A. Sangiovanni Vincentelli “Minimizing production test time to detect faults in analog circuits” in IEEE Trans. CAD, June 1994, falls in the first category since essentially heuristic approaches to test ordering have been proposed. The easiest way to reduce the number of e-tests in a test set is to drop the tests that are never failed [1], however it is necessary to reach a tradeoff between achieving minimal production testing time and maximizing failure information. A large number of papers have tried to adopt a limited set of measurements to predict the results of other measurements, by applying different strategies such as QR factorization [2], singular value decomposition [3], testing of all small subsets of measurements for dependency [4], or selecting measurements based on sensitivity information [5]. These procedures geometrically defined in the space of measurements, or in the space of the statistical SPICE parameters, do not consider circuit specifications. Therefore, e-tests are typically designed to guarantee the range of device parameter variation described by the SPICE corner models rather than considering their statistical correlation with the circuit performance targets.
W. Lindermeir et al., “Analog testing by Characteristic Observation Inference”, IEEE Trans. on CAD, September 1999, suggest that the satisfaction of the specifications can be inferred directly from the measurements. However, their validation criteria exploits posterior probabilities extracted from a training data set, to classify the circuit with respect to one given specification.
K. Kibarian et al. in “Analysis of Mixed-Signal Manufacturability with Statistical Technology CAD (TCAD)”, IEEE Trans. on Semiconductor Manufacturing”, 1996, deals with the introduction of additional e-test or in-line measurements based on a matching algorithm between measurements and process factors, but without considering circuit specifications compliance.
The following documents are incorporated by reference herein in their entireties:
[1] L. Milor and A. Sangiovanni-Vincentelli, “Minimizing Production Test Time to Detect Faults in Analog Circuits”, IEEE Trans. on CAD of ICs and Systems, June 1994, pp. 796–813
[2] G. N. Stenbakken et al., “Test-point selection and testability measures via QR factorization of linear models”, IEEE Trans. Instrum. Measur., Volume: 36, pp. 406–410, June 1987.
[3] E. Liu et al.,Analog Testability analysis and fault diagnosis using behavioral modeling, Proc. CICC, pp. 413–416, 1994.
[4] G. N. Stenbakken et al., Ambiguity Groups and Testability, IEEE Trans. Instrum. Measur., Volume: 38, pp. 941–947, October 1989.
[5] G. J. Heminket al., Testability analysis of analog system, IEEE Trans. Computer-Aided Design, Volume: 9, pp. 573–583, June 1990.